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==Extensions==
 
==Extensions==
 
AMX was introduced by Intel in June 2020 and first supported by Intel with the [[Sapphire Rapids]] [[microarchitecture]] for [[Xeon]] servers, planned for 2021.<ref>{{Cite web|url=https://www.heise.de/news/Intel-AMX-Erste-Informationen-zur-Advanced-Matrix-Extensions-Architecture-4797415.html|title=Intel AMX: Erste Informationen zur Advanced Matrix Extensions Architecture|first=heise|last=online|website=heise online}}</ref><ref>{{Cite web|url=https://www.anandtech.com/show/16921/intel-sapphire-rapids-nextgen-xeon-scalable-gets-a-tiling-upgrade|title=Intel Xeon Sapphire Rapids: How To Go Monolithic with Tiles|first=Dr Ian|last=Cutress|website=[[AnandTech]]}}</ref> It introduced 2-dimensional [[processor register|registers]] called tiles upon which accelerators can perform operations. It is intended as an extensible architecture, the first accelerator implemented is called tile matrix multiply unit (TMUL).<ref>https://software.intel.com/content/dam/develop/public/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf</ref> <ref>{{Cite web|url=https://fuse.wikichip.org/news/3600/the-x86-advanced-matrix-extension-amx-brings-matrix-operations-to-debut-with-sapphire-rapids/|title=The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids|first=David|last=Schor|date=June 29, 2020}}</ref>
 
AMX was introduced by Intel in June 2020 and first supported by Intel with the [[Sapphire Rapids]] [[microarchitecture]] for [[Xeon]] servers, planned for 2021.<ref>{{Cite web|url=https://www.heise.de/news/Intel-AMX-Erste-Informationen-zur-Advanced-Matrix-Extensions-Architecture-4797415.html|title=Intel AMX: Erste Informationen zur Advanced Matrix Extensions Architecture|first=heise|last=online|website=heise online}}</ref><ref>{{Cite web|url=https://www.anandtech.com/show/16921/intel-sapphire-rapids-nextgen-xeon-scalable-gets-a-tiling-upgrade|title=Intel Xeon Sapphire Rapids: How To Go Monolithic with Tiles|first=Dr Ian|last=Cutress|website=[[AnandTech]]}}</ref> It introduced 2-dimensional [[processor register|registers]] called tiles upon which accelerators can perform operations. It is intended as an extensible architecture, the first accelerator implemented is called tile matrix multiply unit (TMUL).<ref>https://software.intel.com/content/dam/develop/public/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf</ref> <ref>{{Cite web|url=https://fuse.wikichip.org/news/3600/the-x86-advanced-matrix-extension-amx-brings-matrix-operations-to-debut-with-sapphire-rapids/|title=The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids|first=David|last=Schor|date=June 29, 2020}}</ref>
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=== Tile matrix multiply unit ===
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TMUL unit supports [[bfloat16 floating-point format|BF16]] and [[INT8]] input types<ref>{{Cite web|url=https://en.wikichip.org/wiki/x86/amx|title=Advanced Matrix Extension (AMX) - x86 - WikiChip|website=en.wikichip.org}}</ref>. The register file consists of 8 tiles, each with 16 rows of size 64-byte (32 BF16 or 64 INT8 values). The only supported operation as for now is [[matrix multiplication|matrix multiplication]] <math> C_{nm} = \sum_{k=1}^K A_{nk}B_{km}. </math> <ref name="iaiseaffpr">{{cite web |url=https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference |title=Intel Architecture Instruction Set Extensions and Future Features Programming Reference |access-date=2021-09-26 |publisher=Intel}}</ref>
  
 
=== Software support ===
 
=== Software support ===
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*Operating system support
 
*Operating system support
 
**[[glibc]] support for detecting AMX feature in CPUs committed at 25 Jun 2020<ref>{{Cite web|url=https://sourceware.org/git/?p=glibc.git;a=commit;h=4fdd4d41a17dda26c854ed935658154a17d4b906|title=x86: Detect Intel Advanced Matrix Extensions|date=2020-07-02|language=en-US|access-date=2020-07-02}}</ref>
 
**[[glibc]] support for detecting AMX feature in CPUs committed at 25 Jun 2020<ref>{{Cite web|url=https://sourceware.org/git/?p=glibc.git;a=commit;h=4fdd4d41a17dda26c854ed935658154a17d4b906|title=x86: Detect Intel Advanced Matrix Extensions|date=2020-07-02|language=en-US|access-date=2020-07-02}}</ref>
**[[Linux kernel]] support is available since [[5.16]]<ref>{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=Linux-FPU-Cleaning-For-AMX|title=Linux x86 FPU Code Getting Reworked In Preparation For Intel AMX - Phoronix|website=[[Phoronix]]}}</ref>
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**[[Linux kernel]] support will not be available until at least 5.16<ref>{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=Linux-FPU-Cleaning-For-AMX|title=Linux x86 FPU Code Getting Reworked In Preparation For Intel AMX - Phoronix|website=[[Phoronix]]}}</ref>
  
 
== References ==
 
== References ==
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* [https://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
 
* [https://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
 
* [https://en.wikichip.org/wiki/x86/amx Wikichip: Advanced Matrix Extension (AMX) - x86]
 
* [https://en.wikichip.org/wiki/x86/amx Wikichip: Advanced Matrix Extension (AMX) - x86]
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{{AMD technology}}
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{{Intel technology}}
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== See also ==
 
== See also ==

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